Educational requirements: Bachelor
English requirements: Competent English
Requirements for skilled employment experience for years: 5-8 years
Required residence status: Temporary visa, Permanent resident, Citizen
Accept remote work: unacceptable
Responsibilities include:
-Chip and block-level design verification -Enhancement of our verification infrastructure and methods -Support of chip team’s verification efforts through to tapeout -Planing, tracking and documentation of verification throughout chip development project -Delivery of large complex projects on time -Running lint checks -Mentoring of junior team members
What we’re looking for:
-15+ years relevant industry experience -MSc in Electrical / Electronics / Communication Engineering or Computer Science -A deep understanding of digital design verification fundamentals including low power and multi-clock-domain design for mass-produced, mixed-signal chips -Willing to think outside of the standard industry approaches -Expert in digital simulation, some experience with design and AMS simulation -Very experienced with the Cadence or Synopsys simulation suites -Experience with coverage collection tools -Experience defining functional verification requirements, implementing tests to meet them -Expert in HDL languages such as Verilog, SystemVerilog or VHDL -Experience with building complex testbench infrastructures -Experience running and debugging gate level simulations in post-PnR netlists with SDF annotation, power-aware simulation experience is a plus -Experience setting up and maintaining continuous integration (CI) flows for regression testing and reporting status -A good understanding of embedded processor systems, familiarity with RISC-V is a plus -Experience writing embedded C and structuring code in a way which makes reusability and maintenance a breeze -Experience with cocotb is a plus -Hands-on experience with Linux development environment staples such as make, shell scripts and Python -Experience using the git revision control tool
