Educational requirements: Bachelor
English requirements: Competent English
Requirements for skilled employment experience for years: 3-5 years
Required residence status: Temporary visa, Permanent resident, Citizen
Accept remote work: unacceptable
Your responsibilities would include:
802.11ah PHY development in Scala, SystemVeriliog and C Implementation of custom instructions in RISC-V architectures Functional verification of 802.11ah PHY in RTL simulators, SDF-annotated gate level simulators and AMS simulators using SystemVerilog, Verilog-A, Matlab, C and Python Work closely with the Systems team to achieve the best performance Work closely with the Analog & RF to define and improve radio interface Work closely with the Firmware team to develop embedded PHY firmware Assist with bring-up of silicon in the lab & debug PHY performance Provide overall technical expertise and brilliance
To be successful in this role, the ideal candidate would have the following skills and experience:
Essential skills (you must have):
MSc in Electrical / Electronics / Communication Engineering or Computer Science 8 years experience as a PHY IC Design Engineer Proven experience developing multiple blocks of 802.11 PHYs in complex SoCs A deep understanding of the IEEE 802.11 PHY layer and familiarity with 802.11ah A deep understanding of digital design fundamentals including low power and multi-clock-domain design Hands-on experience with the Cadence or Synopsys simulation suite Hands-on experience with Linux development environment staples such as make, shell scripts and Python Excellent verbal and written communication skills Proven to work constructively within your team and among other groups Strong analytical and problem-solving skills A determination to deliver even when subject to time pressures A hands-on, practical attitude
Bonus skills (these will make you stand out in your application):
Proven experience performing phy bringup, debug and performance measurement on silicon in the lab A good understanding of embedded processors, familiarity with RISC-V is a plus A solid understanding of mixed signal ASIC design and simulation Experience using the git revision control tool Experience with development and debugging of digital designs from RTL design through to SDF-annotated gatesims
